Sets the doing_mem flag to @status.

Setup per-MF selector state.

Create a new AAMDNode that describes this AAMDNode after applying a constant offset to the start of the pointer.

Check if the packetizer should try to add the given instruction to the current packet. One reasons for which it may not be desirable to include an ins

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. If so then MinSize is set to the mi

Return true if creating a shift of the type by the given amount is not profitable.

Hook for defining which Generic instructions should be CSEd. GISelCSEInfo currently only calls this hook when dealing with generic opcodes.

Returns true if the two given memory operations should be scheduled adjacent. Note that you have to add: DAG->addMutation(createLoadClusterDAGMutation

SrcRC and DstRC will be morphed into NewRC if this returns true.

Return true if CodeGenPrepare should consider splitting large offset of a GEP to make the GEP fit into the addressing mode and can be sunk into the sa

Return true if it is beneficial to convert a load of a constant to just the constant itself. On some targets it might be more efficient to use a combi

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns.

Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'.

Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable

Return true if size-info optimization remark is enabled, false otherwise.

Returns true if all fields of the stack protector descriptor are initialized implying that we should/are ready to emit a stack protector.

Only allow verbose messages if we know we're filtering by hotness (BFI is only set in this case).

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. Default is to never expand.

Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.

There are two general methods for expanding a BUILD_VECTOR node: 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle them together.

Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.

Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a library call is preferred (e.g for code-size reasons)

Returns true if the index type for a masked gather/scatter requires extending

Returns true if arguments should be extended in lib calls.

Return true if it is profitable to fold a pair of shifts into a mask. This is usually true on most targets. But some targets, like Thumb1, have immedi

There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return t

Return true if pulling a binary operation into a select with an identity constant is profitable. This is the inverse of an IR transform. Example: X +

Try to convert math with an overflow comparison into the corresponding DAG node operation. Targets may want to override this independently of whether

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. This should be true for most architectures with weak

Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function.

Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))

Return true if the function should be outlined from by default.

Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, t

Return true if it is profitable to reduce a load to a smaller type. Example: (i16 (trunc (i32 (load x))) -> i16 load x

Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB.

Returns true if VT is a legal index type for masked gathers/scatters on this target

IRDescription is a textual description of the IR unit the pass is running over.

Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.

This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together. On

Returns true if arguments should be sign-extended in lib calls.

Return true if the instruction should be sunk by MachineSink. MachineSink determines on its own whether the instruction is safe to sink; this gives t

Return true if sinking I's operands to the same basic block as I is profitable, e.g. because the operands can be folded into a target instruction duri

Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.

For most targets, an LLVM type must be broken down into multiple smaller types. Usually the halves are ordered according to the endianness but for som

Returns true if lanemasks should be tracked. LaneMask tracking is necessary to reorder independent subregister defs for the same vreg. This has to be

Check if pressure tracking is needed before building the DAG and initializing this strategy. Called after initPolicy.

PostRA scheduling does not track pressure.

Returns true if liveness for register class @p RC should be tracked at the subregister level.

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add %x, (1 << (KeptBits-1))) srcc

Deferred spilling delays the spill insertion of a virtual register after every other allocation. By deferring the spilling, it is sometimes possible t

Last chance recoloring has a high compile time cost especially for targets with a lot of registers. This method is used to decide whether or not \p Vi

Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting

Move the internal MBB iterator but do not update register states.