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Functions12,151 in github.com/capstone-engine/capstone

FunctionAArch64VectorLayoutToString
arch/AArch64/AArch64BaseInfo.h:347
FunctionAArch64_AM_decodeAdvSIMDModImmType1
arch/AArch64/AArch64AddressingModes.h:385
FunctionAArch64_AM_decodeAdvSIMDModImmType11
arch/AArch64/AArch64AddressingModes.h:668
FunctionAArch64_AM_decodeAdvSIMDModImmType12
arch/AArch64/AArch64AddressingModes.h:739
FunctionAArch64_AM_decodeAdvSIMDModImmType2
arch/AArch64/AArch64AddressingModes.h:404
FunctionAArch64_AM_decodeAdvSIMDModImmType3
arch/AArch64/AArch64AddressingModes.h:422
FunctionAArch64_AM_decodeAdvSIMDModImmType4
arch/AArch64/AArch64AddressingModes.h:440
FunctionAArch64_AM_decodeAdvSIMDModImmType5
arch/AArch64/AArch64AddressingModes.h:459
FunctionAArch64_AM_decodeAdvSIMDModImmType6
arch/AArch64/AArch64AddressingModes.h:478
FunctionAArch64_AM_decodeAdvSIMDModImmType7
arch/AArch64/AArch64AddressingModes.h:496
FunctionAArch64_AM_decodeAdvSIMDModImmType8
arch/AArch64/AArch64AddressingModes.h:509
FunctionAArch64_AM_decodeAdvSIMDModImmType9
arch/AArch64/AArch64AddressingModes.h:533
FunctionAArch64_AM_encodeAdvSIMDModImmType1
arch/AArch64/AArch64AddressingModes.h:380
FunctionAArch64_AM_encodeAdvSIMDModImmType10
arch/AArch64/AArch64AddressingModes.h:566
FunctionAArch64_AM_encodeAdvSIMDModImmType11
arch/AArch64/AArch64AddressingModes.h:638
FunctionAArch64_AM_encodeAdvSIMDModImmType12
arch/AArch64/AArch64AddressingModes.h:709
FunctionAArch64_AM_encodeAdvSIMDModImmType2
arch/AArch64/AArch64AddressingModes.h:399
FunctionAArch64_AM_encodeAdvSIMDModImmType3
arch/AArch64/AArch64AddressingModes.h:417
FunctionAArch64_AM_encodeAdvSIMDModImmType4
arch/AArch64/AArch64AddressingModes.h:435
FunctionAArch64_AM_encodeAdvSIMDModImmType5
arch/AArch64/AArch64AddressingModes.h:454
FunctionAArch64_AM_encodeAdvSIMDModImmType6
arch/AArch64/AArch64AddressingModes.h:473
FunctionAArch64_AM_encodeAdvSIMDModImmType7
arch/AArch64/AArch64AddressingModes.h:491
FunctionAArch64_AM_encodeAdvSIMDModImmType8
arch/AArch64/AArch64AddressingModes.h:515
FunctionAArch64_AM_encodeAdvSIMDModImmType9
arch/AArch64/AArch64AddressingModes.h:528
FunctionAArch64_AM_encodeLogicalImmediate
encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size.
arch/AArch64/AArch64AddressingModes.h:269
FunctionAArch64_AM_getArithExtendImm
getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3
arch/AArch64/AArch64AddressingModes.h:164
FunctionAArch64_AM_getMemDoShift
getMemDoShift - Extract the "do shift" flag value for load/store instructions.
arch/AArch64/AArch64AddressingModes.h:172
FunctionAArch64_AM_getMemExtendType
getExtendType - Extract the extend type for the offset operand of loads/stores.
arch/AArch64/AArch64AddressingModes.h:179
FunctionAArch64_AM_getShifterImm
arch/AArch64/AArch64AddressingModes.h:86
FunctionAArch64_AM_isAdvSIMDModImmType1
0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
arch/AArch64/AArch64AddressingModes.h:374
FunctionAArch64_AM_isAdvSIMDModImmType10
aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh cmode: 1110, op: 1
arch/AArch64/AArch64AddressingModes.h:545
FunctionAArch64_AM_isAdvSIMDModImmType11
aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
arch/AArch64/AArch64AddressingModes.h:629
FunctionAArch64_AM_isAdvSIMDModImmType12
aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
arch/AArch64/AArch64AddressingModes.h:702
FunctionAArch64_AM_isAdvSIMDModImmType2
0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
arch/AArch64/AArch64AddressingModes.h:393
FunctionAArch64_AM_isAdvSIMDModImmType3
0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
arch/AArch64/AArch64AddressingModes.h:411
FunctionAArch64_AM_isAdvSIMDModImmType4
abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
arch/AArch64/AArch64AddressingModes.h:429
FunctionAArch64_AM_isAdvSIMDModImmType5
0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
arch/AArch64/AArch64AddressingModes.h:447
FunctionAArch64_AM_isAdvSIMDModImmType6
abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
arch/AArch64/AArch64AddressingModes.h:466
FunctionAArch64_AM_isAdvSIMDModImmType7
0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
arch/AArch64/AArch64AddressingModes.h:485
FunctionAArch64_AM_isAdvSIMDModImmType8
0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
arch/AArch64/AArch64AddressingModes.h:503
FunctionAArch64_AM_isAdvSIMDModImmType9
abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
arch/AArch64/AArch64AddressingModes.h:521
FunctionAArch64_AM_isAnyMOVWMovAlias
arch/AArch64/AArch64AddressingModes.h:932
FunctionAArch64_AM_isSVEMaskOfIdenticalElements64
arch/AArch64/AArch64AddressingModes.h:832
FunctionAArch64_AM_isSVEMoveMaskPreferredLogicalImmediate
Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
arch/AArch64/AArch64AddressingModes.h:869
FunctionAArch64_getFeatureBits
Hacky: enable all features for disassembler
arch/AArch64/AArch64Disassembler.c:208
FunctionAArch64_getInstruction
arch/AArch64/AArch64Disassembler.c:359
FunctionAArch64_get_insn_id
given internal insn id, return public instruction info
arch/AArch64/AArch64Mapping.c:406
FunctionAArch64_global_init
arch/AArch64/AArch64Module.c:13
FunctionAArch64_group_name
arch/AArch64/AArch64Mapping.c:510
FunctionAArch64_insn_name
arch/AArch64/AArch64Mapping.c:449
FunctionAArch64_option
arch/AArch64/AArch64Module.c:35
FunctionAArch64_post_printer
arch/AArch64/AArch64InstPrinter.c:2759
FunctionAArch64_printInst
arch/AArch64/AArch64InstPrinter.c:128
FunctionAArch64_reg_access
arch/AArch64/AArch64Mapping.c:830
FunctionAArch64_reg_name
arch/AArch64/AArch64Mapping.c:381
FunctionARMCC_getOppositeCondition
arch/ARM/ARMBaseInfo.h:52
FunctionARMII_AddrModeToString
arch/ARM/ARMBaseInfo.h:226
FunctionARM_AM_getAMSubModeStr
arch/ARM/ARMAddressingModes.h:74
FunctionARM_AM_getShiftOpcEncoding
arch/ARM/ARMAddressingModes.h:55
FunctionARM_addReg
arch/ARM/ARMInstPrinter.c:3339
FunctionARM_addUserMode
arch/ARM/ARMInstPrinter.c:3348
FunctionARM_addVectorDataSize
arch/ARM/ARMInstPrinter.c:3332
FunctionARM_addVectorDataType
arch/ARM/ARMInstPrinter.c:3325
FunctionARM_getInstruction
arch/ARM/ARMDisassembler.c:958
FunctionARM_get_insn_id
arch/ARM/ARMMapping.c:313
FunctionARM_global_init
arch/ARM/ARMModule.c:13
FunctionARM_group_name
arch/ARM/ARMMapping.c:412
FunctionARM_insn_name
arch/ARM/ARMMapping.c:354
FunctionARM_option
arch/ARM/ARMModule.c:40
FunctionARM_post_printer
arch/ARM/ARMInstPrinter.c:286
FunctionARM_printInst
arch/ARM/ARMInstPrinter.c:450
FunctionARM_reg_access
arch/ARM/ARMMapping.c:498
FunctionARM_reg_name
arch/ARM/ARMMapping.c:245
FunctionARM_reg_name2
arch/ARM/ARMMapping.c:257
MethodAUFoldingSetNode
suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h:250
MethodAccelTable
suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h:199
MethodAccelTableBase
suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h:174
MethodAddAttribute
Adds another set of attribute information to the abbreviation.
suite/synctools/tablegen/include/llvm/CodeGen/DIE.h:109
MethodAddIRPass
suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h:161
MethodAddImplicitConstAttribute
Adds attribute with DW_FORM_implicit_const value
suite/synctools/tablegen/include/llvm/CodeGen/DIE.h:114
MethodAddLiveOutRegInfo
AddLiveOutRegInfo - Adds LiveOutInfo for a register.
suite/synctools/tablegen/include/llvm/CodeGen/FunctionLoweringInfo.h:235
MethodAddMachinePass
suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h:205
MethodAddPromotedToType
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that defa
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:2312
MethodAddrMode
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:2401
MethodAdjEdgeIdSet
suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h:320
MethodAdjustBlockAddressRefCount
Increment the internal refcount of the number of BlockAddresses referencing this BasicBlock by \p Amt. This is almost always 0, sometimes one possibl
suite/synctools/tablegen/include/llvm/IR/BasicBlock.h:559
MethodAdvanceCycle
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot issue in the current cycle, either because of la
suite/synctools/tablegen/include/llvm/CodeGen/ScheduleHazardRecognizer.h:104
MethodAliasScopeNode
suite/synctools/tablegen/include/llvm/IR/Metadata.h:1280
MethodAliasSummary
suite/synctools/tablegen/include/llvm/IR/ModuleSummaryIndex.h:458
MethodAllocateReg
AllocateReg - Attempt to allocate one register. If it is not available, return zero. Otherwise, return the register, marking it and any aliases as a
suite/synctools/tablegen/include/llvm/CodeGen/CallingConvLower.h:351
MethodAllocateRegBlock
AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive registers. If this is not possible, return zero. Otherwise, return the firs
suite/synctools/tablegen/include/llvm/CodeGen/CallingConvLower.h:384
MethodAllocateStack
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
suite/synctools/tablegen/include/llvm/CodeGen/CallingConvLower.h:425
MethodAllowedRegVector
suite/synctools/tablegen/include/llvm/CodeGen/RegAllocPBQP.h:98
MethodAnalysisManager
suite/synctools/tablegen/include/llvm/IR/PassManagerImpl.h:23
MethodAnalysisPassModel
suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h:295
MethodAnalysisResultModel
suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h:200
MethodAnalysisResultModel
suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h:239
MethodAnalyzeArguments
The function will invoke AnalyzeFormalArguments.
suite/synctools/tablegen/include/llvm/CodeGen/CallingConvLower.h:287
MethodAnalyzeArgumentsSecondPass
suite/synctools/tablegen/include/llvm/CodeGen/CallingConvLower.h:532
MethodAnd
suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h:223
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