Build and insert \p Res = G_UITOFP \p Src0

Build and insert \p Res = G_UMAX \p Op0, \p Op1

Build and insert \p Res = G_UMIN \p Op0, \p Op1

Build and insert \p Res = G_UREM \p Op0, \p Op1

Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp

Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1

Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.

Build and insert \p Res = G_VECREDUCE_ADD \p Src

Build and insert \p Res = G_VECREDUCE_AND \p Src

Build and insert \p Res = G_VECREDUCE_FADD \p Src \p ScalarIn is the scalar accumulator input to the reduction operation of \p VecIn.

Build and insert \p Res = G_VECREDUCE_FMAX \p Src

Build and insert \p Res = G_VECREDUCE_FMIN \p Src

Build and insert \p Res = G_VECREDUCE_FMUL \p Src \p ScalarIn is the scalar accumulator input to the reduction operation of \p VecIn.

Build and insert \p Res = G_VECREDUCE_MUL \p Src

Build and insert \p Res = G_VECREDUCE_OR \p Src

Build and insert \p Res = G_VECREDUCE_SMAX \p Src

Build and insert \p Res = G_VECREDUCE_SMIN \p Src

Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn \p ScalarIn is the scalar accumulator input to start the sequential reduction op

Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn \p ScalarIn is the scalar accumulator input to start the sequential reduction op

Build and insert \p Res = G_VECREDUCE_UMAX \p Src

Build and insert \p Res = G_VECREDUCE_UMIN \p Src

Build and insert \p Res = G_VECREDUCE_XOR \p Src

Build and insert \p Res = G_XOR \p Op0, \p Op1

Return true if the bundle operand at index \p OpIdx has the attribute \p A.

Return the end of the list of BundleOpInfo instances associated with this OperandBundleUser.

Return the range [\p bundle_op_info_begin, \p bundle_op_info_end).

Return true if the target can combine store(extractelement VectorTy, Idx). \p Cost[out] gives the cost of that transformation when this is true.

Return true if the given SDNode can be copied during scheduling even if it has glue.

Return true for instructions that can be folded as memory operands in other instructions. The most common use for this is instructions that are simple

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond. When succ

This hook must be implemented to check whether the return values described by \p Outs can fit into the return registers. If false is returned, an sret

Returns true if the tail call can be made conditional on BranchCond.

Check whether this insertion point can be materialized. As soon as ::getPoint is called and thus, the point materialized calling this method does not

Worst case, we need to slice the basic block, but that is still doable.

Returns if it's reasonable to merge stores to MemVT size.

canReserveReg - Returns true if PhysReg can be used as a reserved register. Any register can be reserved before freezeReservedRegs() is called.

Return true if the call can return twice

Returns true if the rounding mode RM may be QRM at compile time or at run time.

canSimplifyCallFramePseudos - When possible, it's best to simplify the call frame pseudo ops before doing frame index elimination. This is possible on

Check whether or not the given \p MBB can be used as a epilogue for the target. The epilogue will be inserted before the first terminator of that bloc

Check whether or not the given \p MBB can be used as a prologue for the target. The prologue will be inserted first in this basic block. This method i

\returns true if emitting a copy from \p Src to \p Dst is impossible.

Determine if the call cannot be duplicated.

Determine if the invoke cannot be duplicated.

Determine if the call cannot be tail merged.

Returns an iterator that points to the default case. Note: this iterator allows to resolve successor only. Attempt to resolve case value causes an ass

Returns a read/write iterator that points one past the last in the SwitchInst.

changeImmediateDominator - This method is used to update the dominator tree information when a node's immediate dominator changes.

Change the top-level loop that contains BB to the specified loop. This should be used by transformations that restructure the loop hierarchy tree.

Replace the specified loop in the top-level loops list with the indicated loop.

Return the type converted to an equivalently sized integer or vector with integer element type. Similar to changeVectorElementTypeToInteger, but also

Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.

Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.

Return true if this shuffle returns a vector with a different number of elements than its source vectors. Examples: shufflevector <4 x n> A, <4 x n> B

A full SizeAndActionsVec must cover all bit sizes, i.e. must start with from size 1.

Does this live virtual register interfere with the union?

A partial SizeAndActionsVec potentially doesn't cover all bit sizes, i.e. it's OK if it doesn't start from size 1.