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Functions12,151 in github.com/capstone-engine/capstone

↓ 3 callersFunctionprintAddress
arch/SystemZ/SystemZInstPrinter.c:42
↓ 3 callersFunctionprintAddressingMode
arch/M68K/M68KInstPrinter.c:131
↓ 3 callersFunctionprintRegName
arch/M680X/M680XInstPrinter.c:102
↓ 3 callersFunctionprintRegName
arch/Mips/MipsInstPrinter.c:150
↓ 3 callersFunctionprintRegbitsRange
arch/M68K/M68KInstPrinter.c:80
↓ 3 callersFunctionprintRegbitsRange
(buffer, data, prefix)
contrib/objdump/objdump-m68k.py:75
↓ 3 callersFunctionprint_insn
(md, code)
bindings/python/tests/test_customized_mnem.py:13
↓ 3 callersFunctionprint_insn
Print one instruction
tests/test_customized_mnem.c:27
↓ 3 callersMethodrbegin
suite/synctools/tablegen/include/llvm/IR/BasicBlock.h:301
↓ 3 callersFunctionread_varuint32
input | code : code pointer start from varuint32 | code_len : start from the code pointer to the end, how long is it | param_size : pointer of the pa
arch/WASM/WASMDisassembler.c:380
↓ 3 callersMethodregisterTargetAnalysis
Target override these hooks to parse target-specific analyses.
suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h:245
↓ 3 callersMethodremove
suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h:568
↓ 3 callersMethodrend
suite/synctools/tablegen/include/llvm/IR/BasicBlock.h:303
↓ 3 callersFunctionreplace_hex
suite/cstest/src/helper.c:108
↓ 3 callersFunctionreplace_negative
suite/cstest/src/helper.c:155
↓ 3 callersMethodrun
(self)
suite/test_group_name.py:22
↓ 3 callersMethodrun
(self)
bindings/python/setup.py:158
↓ 3 callersFunctionrun_mc
(arch, hexcode, option, syntax=None)
suite/test_mc.py:25
↓ 3 callersMethodsetFlag
Set a MI flag.
suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h:335
↓ 3 callersMethodsetIsExact
suite/synctools/tablegen/include/llvm/IR/Operator.h:135
↓ 3 callersMethodsetPointer
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:141
↓ 3 callersMethodsetReductionState
suite/synctools/tablegen/include/llvm/CodeGen/RegAllocPBQP.h:216
↓ 3 callersMethodsetSyntax
(int syntax)
bindings/java/capstone/Capstone.java:467
↓ 3 callersFunctionset_groups
arch/SH/SHDisassembler.c:96
↓ 3 callersMethodsplice
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before 'Where'. If From points to a bundle of instructio
suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h:967
↓ 3 callersMethodsucc_begin
suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h:336
↓ 3 callersMethodsucc_end
suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h:338
↓ 3 callersMethodsucc_size
suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h:348
↓ 3 callersFunctiontranslateRegister
translateRegister - Translates an internal register to the appropriate LLVM register, and appends it as an operand to an MCInst. @param mcInst -
arch/X86/X86Disassembler.c:136
↓ 3 callersMethodtranspose
Matrix transpose.
suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Math.h:205
↓ 3 callersFunctiontryGetInstruction16
arch/TriCore/TriCoreDisassembler.c:1537
↓ 3 callersFunctionupdate_bits_range
arch/M68K/M68KDisassembler.c:3475
↓ 3 callersFunctionupdate_op_reg_list
arch/M68K/M68KDisassembler.c:3494
↓ 3 callersMethoduse_instructions
suite/synctools/tablegen/include/llvm/CodeGen/MachineRegisterInfo.h:484
↓ 3 callersFunctionverifySecFlag
suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h:224
↓ 2 callersFunctionAArch64SysReg_genericRegisterString
NOTE: result must be big enough to contain the result
arch/AArch64/AArch64BaseInfo.c:55
↓ 2 callersFunctionAArch64_AM_getExtendType
getExtendType - Extract the extend type for operands of arithmetic ops.
arch/AArch64/AArch64AddressingModes.h:114
↓ 2 callersFunctionAArch64_AM_getShiftExtendName
getShiftName - Get the string encoding for the shift type.
arch/AArch64/AArch64AddressingModes.h:47
↓ 2 callersFunctionAArch64_AM_processLogicalImmediate
processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size
arch/AArch64/AArch64AddressingModes.h:193
↓ 2 callersFunctionAArch64_map_vregister
map internal raw vregister to 'public' register
arch/AArch64/AArch64Mapping.c:534
↓ 2 callersFunctionARMCC_ARMCondCodeToString
arch/ARM/ARMBaseInfo.h:73
↓ 2 callersFunctionARM_getRegName
arch/ARM/ARMInstPrinter.c:191
↓ 2 callersFunctionAddOrRemoveMetadataToCopy
Add or update the an entry (Kind, MD) to MetadataToCopy, if \p MD is not null. If \p MD is null, remove the entry with \p Kind.
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:101
↓ 2 callersFunctionAddThumb1SBit
Thumb1 instructions don't have explicit S bits. Rather, they implicitly set CPSR. Since it's not represented in the encoding, the auto-generated decod
arch/ARM/ARMDisassembler.c:611
↓ 2 callersFunctionBPF_reg_name
arch/BPF/BPFMapping.c:135
↓ 2 callersFunctionCountTrailingOnes_32
CountTrailingOnes_32 - this function performs the operation of counting the number of ones from the least significant bit to the first zero bit. Ex.
MathExtras.h:210
↓ 2 callersFunctionCountTrailingZeros_64
CountTrailingZeros_64 - This function performs the platform optimal form of counting the number of zeros from the least significant bit to the first o
MathExtras.h:218
↓ 2 callersFunctionCreateAdd
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1211
↓ 2 callersMethodCreateAdd
Add matrixes \p LHS and \p RHS. Support both integer and floating point matrixes.
suite/synctools/tablegen/include/llvm/IR/MatrixBuilder.h:161
↓ 2 callersFunctionCreateExactSDiv
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1285
↓ 2 callersFunctionCreateExactUDiv
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1271
↓ 2 callersFunctionCreateFAdd
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1417
↓ 2 callersFunctionCreateFDiv
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1492
↓ 2 callersFunctionCreateFMul
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1467
↓ 2 callersFunctionCreateFNeg
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1597
↓ 2 callersMethodCreateFNeg
suite/synctools/tablegen/include/llvm/IR/NoFolder.h:176
↓ 2 callersFunctionCreateFRem
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1517
↓ 2 callersFunctionCreateFSub
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1442
↓ 2 callersMethodCreateInsertElement
suite/synctools/tablegen/include/llvm/IR/NoFolder.h:258
↓ 2 callersFunctionCreateSDiv
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1275
↓ 2 callersMethodCreateSDiv
suite/synctools/tablegen/include/llvm/IR/NoFolder.h:109
↓ 2 callersMethodCreateShl
Left shift a fixed-point value by an unsigned integer value. The integer value can be any bit width. \p LHS - The left hand side \p LHSSema - The
suite/synctools/tablegen/include/llvm/IR/FixedPointBuilder.h:341
↓ 2 callersFunctionCreateTrunc
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1878
↓ 2 callersFunctionCreateUDiv
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:1261
↓ 2 callersMethodCreateUDiv
suite/synctools/tablegen/include/llvm/IR/NoFolder.h:102
↓ 2 callersFunctionDecode2RUSBitpInstruction
arch/XCore/XCoreDisassembler.c:551
↓ 2 callersFunctionDecodeAddrMode6Operand
arch/ARM/ARMDisassembler.c:2494
↓ 2 callersFunctionDecodeAddrModeImm12Operand
arch/ARM/ARMDisassembler.c:2377
↓ 2 callersFunctionDecodeFPR16RegisterClass
arch/AArch64/AArch64Disassembler.c:461
↓ 2 callersFunctionDecodeFPR8RegisterClass
arch/AArch64/AArch64Disassembler.c:485
↓ 2 callersFunctionDecodeGPR32RegisterClass
arch/Mips/MipsDisassembler.c:872
↓ 2 callersFunctionDecodeGPRMM16RegisterClass
arch/Mips/MipsDisassembler.c:833
↓ 2 callersFunctionDecodeGPRPairRegisterClass
arch/ARM/ARMDisassembler.c:1030
↓ 2 callersFunctionDecodeGPRSeqPairsClassRegisterClass
arch/AArch64/AArch64Disassembler.c:2115
↓ 2 callersFunctionDecodeL2OpInstructionFail
arch/XCore/XCoreDisassembler.c:409
↓ 2 callersFunctionDecodeL2RUSInstruction
arch/XCore/XCoreDisassembler.c:596
↓ 2 callersFunctionDecodeL5RInstructionFail
arch/XCore/XCoreDisassembler.c:648
↓ 2 callersFunctionDecodeSORegMemOperand
arch/ARM/ARMDisassembler.c:1711
↓ 2 callersFunctionDecodeT2AddrModeImm8s4
arch/ARM/ARMDisassembler.c:3957
↓ 2 callersFunctionDiffListIterator_getVal
MCRegisterInfo.c:59
↓ 2 callersFunctionDiffListIterator_init
MCRegisterInfo.c:53
↓ 2 callersFunctionDiffListIterator_isValid
MCRegisterInfo.c:81
↓ 2 callersFunctionGetInsertBlock
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:177
↓ 2 callersFunctionGetInsertPoint
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:178
↓ 2 callersFunctionITStatus_advanceITState
Advances the IT block state to the next T or E
arch/ARM/ARMDisassembler.c:83
↓ 2 callersFunctionITStatus_getITCC
Returns the condition code for instruction in IT block
arch/ARM/ARMDisassembler.c:71
↓ 2 callersFunctionLog2_32_Ceil
Log2_32_Ceil - This function returns the ceil log base 2 of the specified value, 32 if the value is zero. (32 bit edition). Ex. Log2_32_Ceil(32) == 5,
MathExtras.h:286
↓ 2 callersFunctionMCInst_getOpcodePub
MCInst.c:74
↓ 2 callersFunctionMCOperand_CreateImm1
MCInst.c:187
↓ 2 callersFunctionMCOperand_setReg
setReg - Set the register number.
MCInst.c:141
↓ 2 callersFunctionMCRegisterClass_contains
MCRegisterInfo.c:134
↓ 2 callersFunctionMCRegisterInfo_getMatchingSuperReg
MCRegisterInfo.c:86
↓ 2 callersMethodReset
Reset - This callback is invoked when a new block of instructions is about to be schedule. The hazard state should be set to an initialized state.
suite/synctools/tablegen/include/llvm/CodeGen/ScheduleHazardRecognizer.h:67
↓ 2 callersFunctionSetCurrentDebugLocation
Set location information used by debugging information.
suite/synctools/tablegen/include/llvm/IR/IRBuilder.h:207
↓ 2 callersFunctionUsage
(s)
suite/cstest/cstest_report.py:13
↓ 2 callersFunctionX86_get_op_access
given internal insn id, return operand access info
arch/X86/X86Mapping.c:2213
↓ 2 callersFunctionX86_lockrep
return true if we patch the mnemonic
arch/X86/X86Mapping.c:1988
↓ 2 callersMethod__str__
(self)
bindings/python/capstone/__init__.py:518
↓ 2 callersFunction_cs_disasm
bindings/ocaml/ocaml.c:28
↓ 2 callersMethodaddAttribute
Add attribute to this global.
suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h:187
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