Return true if the named field is unset.

isVarArg - Return true if this function takes a variable number of arguments.

Returns true if the specified index corresponds to a variable sized object.

Return true if this instruction can have a variable number of operands. In this case, the variable operands will be after the normal operands but befo

Similar to isShuffleMaskLegal. Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a consta

Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. On x86 before AVX2

Return true if assembly output should contain comments.

Return true if the specified register number is in the virtual register namespace.

Return true if this is a load from a volatile memory location.

Return true if this is a store to a volatile memory location.

Return true if this is a cmpxchg from a volatile memory location.

Return true if this is a RMW on a volatile memory location.

Returns true if the attached MachineMemOpeand as the volatile flag set.

Return true if this cmpxchg may spuriously fail.

Tests if this a weak dependence. Weak dependencies are considered DAG edges for height computation and other heuristics, but do not force ordering. Br

Whether the definition of this global may be replaced at link time. NB: Using this method outside of the code generators is almost always a mistake:

Return true if this is X86 AMX.

Return true if this is x86 long double.

Return true if this is X86 MMX.

Returns true if the specified node is a ZEXTLOAD.

This is just a convenience method to make client code smaller for a common code. It also correctly performs the comparison without the potential for a

Return true if the value is positive or negative zero.

Return true for pseudo instructions that don't consume any machine resources in their current form. These are common cases that the scheduler should c

Return true if all elements of this shuffle are the same value as the first element of exactly one source vector without changing the length of that v

Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget. This function also sets bits in Mask related to input operands

Returns true if the live range is zero length, i.e. no live segments span instructions. It doesn't pay to spill such a range.

Test if the given EVT has zero size, this will fail if called on a scalable type

Target-specific combining of register parts into its original value

Return true if the target wants to keep the frame pointer regardless of the function attribute "frame-pointer".

Whether bits in a BitsInit should stay unresolved if resolving them would result in a ? (UnsetInit). This behavior is used to represent instruction en

Return true if the MachineInstr kills the specified register. If TargetRegisterInfo is passed, then it also checks if there is a kill of a super-regis

Return true if we know at compile time this has more than or the same bits as VT.

Return true if we know at compile time this has more bits than VT.

Return true if we know at compile time this has fewer than or the same bits as VT.

Return true if we know at compile time this has fewer bits than VT.

leaveSSA - Indicates that the machine function is no longer in SSA form.

Loop over all of the value types that can be represented by values in the given register class.

Called for instructions with the Custom LegalizationAction.

\returns true if MI is either legal or has been legalized and false if not legal. Return true if MI is either legal or has been legalized and false if

Return linkage type recorded for this global value.

live_begin/live_end - Iterators for live roots at a given safe point.

Unlike livein_begin, this method does not check that the liveness information is accurate. Still for debug purposes it may be useful to have iterators

Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine

Looks through copy instructions and returns the actual source register.

This method finds the value with the given \p Name in the the symbol table. @returns the value associated with the \p Name Lookup a named Value.

handler for CPU12 DBEQ/DNBE/IBEQ/IBNE/TBEQ/TBNE instructions. Example: DBNE X,$1000

Should SelectionDAG lower an atomic load of the given kind as a normal LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to eventual

Should SelectionDAG lower an atomic store of the given kind as a normal StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to eventu

This hook must be implemented to lower the given call instruction, including argument and return value marshalling. \return true if the lowering suc

This hook must be implemented to lower the incoming (formal) arguments, described by \p VRegs, for GlobalISel. Each argument must end up in the relate

On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.

Lower an interleaved load to target specific intrinsics. Return true on success. \p LI is the vector load instruction. \p Shuffles is the shufflevect

Lower an interleaved store to target specific intrinsics. Return true on success. \p SI is the vector store instruction. \p SVI is the shufflevector