| 3889 | } |
| 3890 | |
| 3891 | static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, |
| 3892 | uint64_t Address, const void* Decoder) |
| 3893 | { |
| 3894 | DecodeStatus S = MCDisassembler_Success; |
| 3895 | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
| 3896 | unsigned U = fieldFromInstruction_4(Insn, 23, 1); |
| 3897 | int imm = fieldFromInstruction_4(Insn, 0, 12); |
| 3898 | bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); |
| 3899 | |
| 3900 | if (Rt == 15) { |
| 3901 | switch (MCInst_getOpcode(Inst)) { |
| 3902 | case ARM_t2LDRBpci: |
| 3903 | case ARM_t2LDRHpci: |
| 3904 | MCInst_setOpcode(Inst, ARM_t2PLDpci); |
| 3905 | break; |
| 3906 | case ARM_t2LDRSBpci: |
| 3907 | MCInst_setOpcode(Inst, ARM_t2PLIpci); |
| 3908 | break; |
| 3909 | case ARM_t2LDRSHpci: |
| 3910 | return MCDisassembler_Fail; |
| 3911 | default: |
| 3912 | break; |
| 3913 | } |
| 3914 | } |
| 3915 | |
| 3916 | switch(MCInst_getOpcode(Inst)) { |
| 3917 | case ARM_t2PLDpci: |
| 3918 | break; |
| 3919 | case ARM_t2PLIpci: |
| 3920 | if (!hasV7Ops) |
| 3921 | return MCDisassembler_Fail; |
| 3922 | break; |
| 3923 | default: |
| 3924 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 3925 | return MCDisassembler_Fail; |
| 3926 | } |
| 3927 | |
| 3928 | if (!U) { |
| 3929 | // Special case for #-0. |
| 3930 | if (imm == 0) |
| 3931 | imm = INT32_MIN; |
| 3932 | else |
| 3933 | imm = -imm; |
| 3934 | } |
| 3935 | |
| 3936 | MCOperand_CreateImm0(Inst, imm); |
| 3937 | |
| 3938 | return S; |
| 3939 | } |
| 3940 | |
| 3941 | static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, |
| 3942 | uint64_t Address, const void *Decoder) |
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