| 482 | } |
| 483 | |
| 484 | static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm, |
| 485 | int64_t Address, const void *Decoder) |
| 486 | { |
| 487 | // Decode the spe2disp field (imm, reg), which has the low 5-bits as the |
| 488 | // displacement with 2-byte aligned, and the next 5 bits as the register #. |
| 489 | |
| 490 | uint64_t Base = Imm >> 5; |
| 491 | uint64_t Disp = Imm & 0x1F; |
| 492 | |
| 493 | // assert(Base < 32 && "Invalid base register"); |
| 494 | if (Base >= 32) |
| 495 | return MCDisassembler_Fail; |
| 496 | |
| 497 | MCOperand_CreateImm0(Inst, Disp << 1); |
| 498 | MCOperand_CreateReg0(Inst, GP0Regs[Base]); |
| 499 | |
| 500 | return MCDisassembler_Success; |
| 501 | } |
| 502 | |
| 503 | static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm, |
| 504 | int64_t Address, const void *Decoder) |
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