| 463 | } |
| 464 | |
| 465 | static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm, |
| 466 | int64_t Address, const void *Decoder) |
| 467 | { |
| 468 | // Decode the spe4disp field (imm, reg), which has the low 5-bits as the |
| 469 | // displacement with 4-byte aligned, and the next 5 bits as the register #. |
| 470 | |
| 471 | uint64_t Base = Imm >> 5; |
| 472 | uint64_t Disp = Imm & 0x1F; |
| 473 | |
| 474 | // assert(Base < 32 && "Invalid base register"); |
| 475 | if (Base >= 32) |
| 476 | return MCDisassembler_Fail; |
| 477 | |
| 478 | MCOperand_CreateImm0(Inst, Disp << 2); |
| 479 | MCOperand_CreateReg0(Inst, GP0Regs[Base]); |
| 480 | |
| 481 | return MCDisassembler_Success; |
| 482 | } |
| 483 | |
| 484 | static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm, |
| 485 | int64_t Address, const void *Decoder) |
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