| 444 | } |
| 445 | |
| 446 | static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm, |
| 447 | int64_t Address, const void *Decoder) |
| 448 | { |
| 449 | // Decode the spe8disp field (imm, reg), which has the low 5-bits as the |
| 450 | // displacement with 8-byte aligned, and the next 5 bits as the register #. |
| 451 | |
| 452 | uint64_t Base = Imm >> 5; |
| 453 | uint64_t Disp = Imm & 0x1F; |
| 454 | |
| 455 | // assert(Base < 32 && "Invalid base register"); |
| 456 | if (Base >= 32) |
| 457 | return MCDisassembler_Fail; |
| 458 | |
| 459 | MCOperand_CreateImm0(Inst, Disp << 3); |
| 460 | MCOperand_CreateReg0(Inst, GP0Regs[Base]); |
| 461 | |
| 462 | return MCDisassembler_Success; |
| 463 | } |
| 464 | |
| 465 | static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm, |
| 466 | int64_t Address, const void *Decoder) |
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