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Function readOpcodeRegister

arch/X86/X86DisassemblerDecoder.c:1741–1776  ·  view source on GitHub ↗

* readOpcodeRegister - Reads an operand from the opcode field of an * instruction and interprets it appropriately given the operand width. * Handles AddRegFrm instructions. * * @param insn - the instruction whose opcode field is to be read. * @param size - The width (in bytes) of the register being specified. * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means

Source from the content-addressed store, hash-verified

1739 * @return - 0 on success; nonzero otherwise.
1740 */
1741static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size)
1742{
1743 if (size == 0)
1744 size = insn->registerSize;
1745
1746 switch (size) {
1747 case 1:
1748 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1749 | (insn->opcode & 7)));
1750 if (insn->rexPrefix &&
1751 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1752 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1753 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1754 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1755 }
1756
1757 break;
1758 case 2:
1759 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1760 + ((bFromREX(insn->rexPrefix) << 3)
1761 | (insn->opcode & 7)));
1762 break;
1763 case 4:
1764 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1765 + ((bFromREX(insn->rexPrefix) << 3)
1766 | (insn->opcode & 7)));
1767 break;
1768 case 8:
1769 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1770 + ((bFromREX(insn->rexPrefix) << 3)
1771 | (insn->opcode & 7)));
1772 break;
1773 }
1774
1775 return 0;
1776}
1777
1778/*
1779 * readImmediate - Consumes an immediate operand from an instruction, given the

Callers 1

readOperandsFunction · 0.85

Calls

no outgoing calls

Tested by

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