/ 64
| 219 | } |
| 220 | //// 64 |
| 221 | NPY_FINLINE npyv_s64 npyv_load_till_s64(const npy_int64 *ptr, npy_uintp nlane, npy_int64 fill) |
| 222 | { |
| 223 | assert(nlane > 0); |
| 224 | const __m256i vfill = npyv_setall_s64(fill); |
| 225 | const __m256i steps = npyv_set_s64(0, 1, 2, 3); |
| 226 | __m256i vnlane = npyv_setall_s64(nlane > 4 ? 4 : (int)nlane); |
| 227 | __m256i mask = _mm256_cmpgt_epi64(vnlane, steps); |
| 228 | __m256i payload = _mm256_maskload_epi64((const long long*)ptr, mask); |
| 229 | __m256i ret = _mm256_blendv_epi8(vfill, payload, mask); |
| 230 | #if NPY_SIMD_GUARD_PARTIAL_LOAD |
| 231 | volatile __m256i workaround = ret; |
| 232 | ret = _mm256_or_si256(workaround, ret); |
| 233 | #endif |
| 234 | return ret; |
| 235 | } |
| 236 | // fill zero to rest lanes |
| 237 | NPY_FINLINE npyv_s64 npyv_load_tillz_s64(const npy_int64 *ptr, npy_uintp nlane) |
| 238 | { |
nothing calls this directly
no test coverage detected