Function npyv_loadn_till_s32

numpy/core/src/common/simd/sse/memory.h:311–349

* Non-contiguous partial load *********************************/ / 32

 *********************************/
//// 32
NPY_FINLINE npyv_s32
npyv_loadn_till_s32(const npy_int32 *ptr, npy_intp stride, npy_uintp nlane, npy_int32 fill)
{
    assert(nlane > 0);
    __m128i vfill = npyv_setall_s32(fill);
    #ifndef NPY_HAVE_SSE41
        const short *wptr = (const short*)ptr;
    #endif
    switch(nlane) {
    #ifdef NPY_HAVE_SSE41
        case 3:
            vfill = _mm_insert_epi32(vfill, ptr[stride*2], 2);
        case 2:
            vfill = _mm_insert_epi32(vfill, ptr[stride], 1);
        case 1:
            vfill = _mm_insert_epi32(vfill, ptr[0], 0);
            break;
    #else
        case 3:
            vfill = _mm_unpacklo_epi32(_mm_cvtsi32_si128(ptr[stride*2]), vfill);
        case 2:
            vfill = _mm_unpacklo_epi64(_mm_unpacklo_epi32(
                _mm_cvtsi32_si128(*ptr), _mm_cvtsi32_si128(ptr[stride])
            ), vfill);
            break;
        case 1:
            vfill = _mm_insert_epi16(vfill, wptr[0], 0);
            vfill = _mm_insert_epi16(vfill, wptr[1], 1);
            break;
    #endif // NPY_HAVE_SSE41
    default:
        return npyv_loadn_s32(ptr, stride);
    } // switch
#if NPY_SIMD_GUARD_PARTIAL_LOAD
    volatile __m128i workaround = vfill;
    vfill = _mm_or_si128(workaround, vfill);
#endif
    return vfill;
}
// fill zero to rest lanes
NPY_FINLINE npyv_s32
npyv_loadn_tillz_s32(const npy_int32 *ptr, npy_intp stride, npy_uintp nlane)