| 174 | // truncate compatible with all compilers(internal use for now) |
| 175 | #if NPY_SIMD_F32 |
| 176 | NPY_FINLINE npyv_s32 npyv__trunc_s32_f32(npyv_f32 a) |
| 177 | { |
| 178 | #ifdef NPY_HAVE_VXE2 |
| 179 | return vec_signed(a); |
| 180 | #elif defined(NPY_HAVE_VXE) |
| 181 | return vec_packs(vec_signed(npyv_doublee(vec_mergeh(a,a))), |
| 182 | vec_signed(npyv_doublee(vec_mergel(a, a)))); |
| 183 | // VSX |
| 184 | #elif defined(__IBMC__) |
| 185 | return vec_cts(a, 0); |
| 186 | #elif defined(__clang__) |
| 187 | /** |
| 188 | * old versions of CLANG doesn't support %x<n> in the inline asm template |
| 189 | * which fixes register number when using any of the register constraints wa, wd, wf. |
| 190 | * therefore, we count on built-in functions. |
| 191 | */ |
| 192 | return __builtin_convertvector(a, npyv_s32); |
| 193 | #else // gcc |
| 194 | npyv_s32 ret; |
| 195 | __asm__ ("xvcvspsxws %x0,%x1" : "=wa" (ret) : "wa" (a)); |
| 196 | return ret; |
| 197 | #endif |
| 198 | } |
| 199 | #endif |
| 200 | |
| 201 | NPY_FINLINE npyv_s32 npyv__trunc_s32_f64(npyv_f64 a, npyv_f64 b) |
no outgoing calls
no test coverage detected