| 199 | #endif |
| 200 | |
| 201 | NPY_FINLINE npyv_s32 npyv__trunc_s32_f64(npyv_f64 a, npyv_f64 b) |
| 202 | { |
| 203 | #ifdef NPY_HAVE_VX |
| 204 | return vec_packs(vec_signed(a), vec_signed(b)); |
| 205 | // VSX |
| 206 | #elif defined(__IBMC__) |
| 207 | const npyv_u8 seq_even = npyv_set_u8(0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27); |
| 208 | // unfortunately, XLC missing asm register vsx fixer |
| 209 | // hopefully, xlc can optimize around big-endian compatibility |
| 210 | npyv_s32 lo_even = vec_cts(a, 0); |
| 211 | npyv_s32 hi_even = vec_cts(b, 0); |
| 212 | return vec_perm(lo_even, hi_even, seq_even); |
| 213 | #else |
| 214 | const npyv_u8 seq_odd = npyv_set_u8(4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31); |
| 215 | #ifdef __clang__ |
| 216 | // __builtin_convertvector doesn't support this conversion on wide range of versions |
| 217 | // fortunately, almost all versions have direct builtin of 'xvcvdpsxws' |
| 218 | npyv_s32 lo_odd = __builtin_vsx_xvcvdpsxws(a); |
| 219 | npyv_s32 hi_odd = __builtin_vsx_xvcvdpsxws(b); |
| 220 | #else // gcc |
| 221 | npyv_s32 lo_odd, hi_odd; |
| 222 | __asm__ ("xvcvdpsxws %x0,%x1" : "=wa" (lo_odd) : "wa" (a)); |
| 223 | __asm__ ("xvcvdpsxws %x0,%x1" : "=wa" (hi_odd) : "wa" (b)); |
| 224 | #endif |
| 225 | return vec_perm(lo_odd, hi_odd, seq_odd); |
| 226 | #endif |
| 227 | } |
| 228 | |
| 229 | // round to nearest integer (assuming even) |
| 230 | #if NPY_SIMD_F32 |
no outgoing calls
no test coverage detected