fill zero to rest lanes
| 264 | } |
| 265 | // fill zero to rest lanes |
| 266 | NPY_FINLINE npyv_s64 npyv_load_tillz_s64(const npy_int64 *ptr, npy_uintp nlane) |
| 267 | { |
| 268 | #ifdef NPY_HAVE_VX |
| 269 | unsigned blane = (nlane > 2) ? 2 : nlane; |
| 270 | return vec_load_len((const signed long long*)ptr, blane*8-1); |
| 271 | #else |
| 272 | return npyv_load_till_s64(ptr, nlane, 0); |
| 273 | #endif |
| 274 | } |
| 275 | //// 64-bit nlane |
| 276 | NPY_FINLINE npyv_s32 npyv_load2_till_s32(const npy_int32 *ptr, npy_uintp nlane, |
| 277 | npy_int32 fill_lo, npy_int32 fill_hi) |
no test coverage detected