Get a constant integer value.

Fetch the type representing a 16-bit integer.

Returns the Intrinsic::ID for this instruction. \pre Must have an intrinsic ID operand.

For example, EQ -> NE, UGT -> ULE, SLT -> SGE, OEQ -> UNE, UGT -> OLE, OLT -> UGE, etc. @returns the inverse predicate for the instruction's current p

Maximum number of micro-ops that may be scheduled per cycle.

Return the number of instructions in this Candidate.

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other c

A helper function that returns the pointer operand of a load or store instruction. Returns nullptr if not load or store.

Return the innermost loop that BB lives in. If a basic block is in no loop (for example the entry node), null is returned.

Return target specific asm information.

The mobility function, which the number of slots in which an instruction may be scheduled.

getMachineFunction - Return the last machine function computed.

Retrieves the GVMaterializer, if any, for this Module.

Return the memory type of the memory reference. This should only be relied on for GlobalISel G_* operation legalization.

Multiply number of micro-ops by this factor to normalize it relative to other resources.

Get the minimum number of elements in this vector. The actual number of elements in the vector is an integer multiple of this value.

Get the next SDUse in the use list.

Returns the next non-null index, if one exists. Otherwise returns getLastIndex().

getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment requirements.

static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1)

getNode - return the (Post)DominatorTree node for the specified basic block. This is the same as using operator[] on this class.

Returns the total number of definitions.

Return the number of operand bundles associated with this User.

Returns the number of source registers.

Return the number of stages contained in this schedule, which is the largest stage index + 1.

Return the number of values defined/returned by this operator.

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFunction yet, in which case this will return -1.

Returns the hash of the original name, it is identical to the GUID for externally visible symbols, but not for local ones.

Extract the byval type for a call or parameter.

Extract the number of dereferenceable bytes for a call or parameter (0=unknown).

Extract the number of dereferenceable_or_null bytes for a parameter (0=unknown).

Extract the preallocated type for a call or parameter.

Extract the preallocated type for a call or parameter.

Parameter type accessors.

Accessor Methods for CatchSwitch stmt

Return a raw pointer that uniquely identifies this attribute.

Get the register for the operand index. The operand at the index should be a register (asserted by MachineOperand).

Return the register class of the specified virtual register. This shouldn't be used directly unless \p Reg has a register class. \see getRegClassOrNul

getRegMask - Returns a bit mask of registers preserved by this RegMask operand.

getRegisterInfo - If register information is available, return it. If not, return null.

Provide an ordered list of schedule DAG mutations for the machine pipeliner.

getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immediate operand, return the 12-bit encoding for it.

Returns the Section this function belongs to.

Returns the section ID of this basic block.

Return the mask for this instruction as a vector of integers. Undefined elements of the mask are returned as UndefMaskElem.

If this set contains a single element, return it, otherwise return null.

Returns the slot for this SlotIndex.

Return the stage that MI is scheduled in, or -1.

Return the start index of this candidate.

Return the number of bytes overwritten by a store of the specified value type. If the value type is a scalable vector type, the scalable property wil

I.e., the representation of the memory from left to right at the bit level looks like: [31 30 ... 1 0] [ 63 62 ... 33 32] ... [ XXX NumRegClasses NumR

Return the human-readable symbolic target-specific name for the specified SubRegIndex.

Return the atomic ordering requirements for this memory operation. For cmpxchg atomic operations, return the atomic ordering requirements when store o

Returns a 0-terminated list of sub-register indices that project some super-register class into this register class. The list has an entry for each Id

For example, EQ->EQ, SLE->SGE, ULT->UGT, OEQ->OEQ, ULE->UGE, OLT->OGT, etc. @returns the predicate that would be the result of exchanging the two oper

getT2SOImmValRotateVal - Return the 12-bit encoded representation if the specified value is a rotated 8-bit value. Return -1 if no rotation encoding i

getTag - Return an opaque tag representing the current state of the union.