Clear any flags in this flag set that aren't also set in Flags. All flags will be cleared if Flags are undefined.

Returns a value representing an invalid (non-existent) node.

When invalidation occurs, remove any registered invalidation events.

The model bases invalidation solely on being in the preserved set. FIXME: We should actually use two different concepts for analysis results rather t

Invalidate resource information.

Invalidate depth resources when some block above this one has changed.

Invalidate height resources when a block below this one has changed.

invalidateLiveness - Indicates that register liveness is no longer being tracked accurately. This should be called by late passes that invalidate the

Mark instruction ordering invalid. Done on every instruction insert.

Invalidate cached interference queries after modifying virtual register live ranges. Interference checks may return stale information unless caches ar

Return true if this is a 1024-bit vector type.

Return true if this is a 1024-bit vector type.

Return true if this is a 128-bit vector type.

Return true if this is a 128-bit vector type.

Return true if this is a 16-bit vector type.

Return true if this is a 16-bit vector type.

Return true if this is a 2048-bit vector type.

Return true if this is a 2048-bit vector type.

Return true if this is a 256-bit vector type.

Return true if this is a 256-bit vector type.

Return true if this is a 32-bit vector type.

Return true if this is a 32-bit vector type.

Return true if this is a 512-bit vector type.

Return true if this is a 512-bit vector type.

Return true if this is a 64-bit vector type.

Return true if this is a 64-bit vector type.

isARMLowRegister - Returns true if the register is a low register (r0-r7).

Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.

If the specific machine instruction is an instruction that adds an immediate value and a physical register, and stores the result in the given physica

Does this describe the address of a local variable. True for dbg.addr and dbg.declare, but not dbg.value, which describes its value.

Return true if the type is an aggregate type. This means it is valid as the first operand of an insertvalue or extractvalue instruction. This includes

Returns true if the specified index corresponds to an object that might be pointed to by an LLVM IR value.

NOTE: This is soft-deprecated. Please use `isAllOnes()` instead.

Return true if this register class may be used to create virtual registers.

isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been reserved. Allocatable registers may show up in

isAllocated - Return true if the specified register (or an alias) is allocated.

Return true if this is an arithmetic shift right.

True if this is an instance of ArrayType.

Returns true if this instruction has the same cost (or less) than a move instruction. This is useful during certain types of optimizations (e.g., rema

Return true if the instruction is as cheap as a move instruction. Targets for different archs need to override this, and different micro-architecture

Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint, will be preserved across the statement.

returns true if the specified virtual register is not mapped to a stack slot or rematerialized.

Tests if this is a Data dependence that is associated with a register.

Return true when \P Inst is both associative and commutative.

Checks if the intrinsic is an annotation.

Returns true if this operation has an atomic ordering requirement of unordered or higher, false otherwise.

Returns true if the attached MachineMemOperand has the atomic flag set.

Return true if this is 'bfloat', a 16-bit bfloat type.

Return true if the dependence is a back-edge in the data dependence graph. Since the DAG doesn't contain cycles, we represent a cycle in the graph usi

Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional

Tests if this is an Order dependence that is marked as a barrier.

True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it. This can be implemented to preve

Returns true if this block begins any section.

Return true if the node is a math/logic binary operator.

Return true if this instruction is a bitcast instruction.

Determine if the Opcode is and/or/xor.

isBlockAddress - Tests if this is a MO_BlockAddress operand.

Boundary nodes are placeholders for the boundary of the scheduling region. BoundaryNodes can have DAG edges, including Data edges, but they do not co

Returns true if this is a conditional, unconditional, or indirect branch. Predicates below can be used to discriminate between these cases, and the Ta

\returns true if a branch from an instruction with opcode \p BranchOpc bytes is capable of jumping to a position \p BrOffset bytes away.

Return true if the operand at index \p Idx is a bundle operand.

Determine whether this argument is passed by value.

Return true if the bit size is a multiple of 8.

Return true if this is a "cfguardtarget" operand bundle.