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Functions
12,151 in github.com/capstone-engine/capstone
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Functions
12,151
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Types & classes
3,652
Method
isRestored
suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h:72
Method
isReturnAddressTaken
This method may be called any time after instruction selection is complete to determine if there is a call to \@llvm.returnaddress in this function.
suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h:373
Method
isReturnBlock
Convenience function that returns true if the block ends in a return instruction.
suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h:822
Method
isReturned
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:120
Method
isReverse
Return true if this shuffle swaps the order of elements from exactly one source vector. Example: shufflevector <4 x n> A, <4 x n> B, <3,undef,1,undef>
suite/synctools/tablegen/include/llvm/IR/Instructions.h:2211
Method
isReverseMask
suite/synctools/tablegen/include/llvm/IR/Instructions.h:2200
Method
isRound
Return true if the size is a power-of-two number of bytes.
suite/synctools/tablegen/include/llvm/CodeGen/ValueTypes.h:221
Method
isSDNodeAlwaysUniform
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:3314
Method
isSDNodeSourceOfDivergence
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:3297
Function
isSEXTLoad
Returns true if the specified node is a SEXTLOAD.
suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h:2930
Method
isSExt
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:75
Method
isSExtCheaperThanZExt
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:2652
Function
isSOImmTwoPartVal
isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVal's.
arch/ARM/ARMAddressingModes.h:203
Method
isSRet
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:81
Method
isSSA
isSSA - Returns true when the machine function is in SSA form. Early passes require the machine function to be in SSA form where every virtual registe
suite/synctools/tablegen/include/llvm/CodeGen/MachineRegisterInfo.h:185
Method
isSafeMemOpType
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. This is mostly true for all types except for so
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:1752
Method
isSafeToMoveRegClassDefs
Return true if it's safe to move a machine instruction that defines the specified register class.
suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h:1490
Method
isSameInstr
isSameInstr - Return true if A and B refer to the same instruction.
suite/synctools/tablegen/include/llvm/CodeGen/SlotIndexes.h:197
Function
isScalarInteger
Return true if this is an integer, not including vectors.
cs_simple_types.h:358
Method
isScalarInteger
Return true if this is an integer, but not a vector.
suite/synctools/tablegen/include/llvm/CodeGen/ValueTypes.h:150
Method
isScavengingFrameIndex
Query whether a frame index is a scavenging frame index.
suite/synctools/tablegen/include/llvm/CodeGen/RegisterScavenging.h:128
Method
isScheduledAtStage
Return true if the instruction is scheduled at the specified stage.
suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h:557
Method
isSecArgPass
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:114
Method
isSelect
Return true if this shuffle chooses elements from its source vectors without lane crossings and all operands have the same number of elements. In othe
suite/synctools/tablegen/include/llvm/IR/Instructions.h:2191
Method
isSelectMask
suite/synctools/tablegen/include/llvm/IR/Instructions.h:2176
Method
isSelectSupported
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:423
Method
isSequential
suite/synctools/tablegen/include/llvm/IR/GetElementPtrTypeIterator.h:112
Method
isShapeMapEmpty
suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h:114
Method
isShift
suite/synctools/tablegen/include/llvm/IR/Instruction.h:165
Function
isShiftedMask_32
isShiftedMask_32 - This function returns true if the argument contains a sequence of ones with the remainder zero (32 bit version.) Ex. isShiftedMask_
MathExtras.h:75
Method
isShuffleMask
suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h:354
Method
isShuffleMaskLegal
Targets can use this to indicate that they only support *some VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:1056
Method
isSigned
Whether the intrinsic is signed or unsigned.
suite/synctools/tablegen/include/llvm/IR/IntrinsicInst.h:554
Function
isSignedIntSetCC
Return true if this is a setcc instruction that performs a signed comparison when used with integer operands.
suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h:1403
Method
isSimple
suite/synctools/tablegen/include/llvm/IR/Instructions.h:261
Method
isSimple
suite/synctools/tablegen/include/llvm/IR/Instructions.h:392
Method
isSimple
Returns true if the memory operation is neither atomic or volatile.
suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h:1333
Method
isSimple
Returns true if the memory operation is neither atomic or volatile.
suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h:53
Function
isSingleElement
Return true if this set contains exactly one member.
suite/synctools/tablegen/include/llvm/IR/ConstantRange.h:261
Method
isSingleSource
Return true if this shuffle chooses elements from exactly one source vector without changing the length of that vector. Example: shufflevector <4 x n>
suite/synctools/tablegen/include/llvm/IR/Instructions.h:2129
Method
isSingleSourceMask
suite/synctools/tablegen/include/llvm/IR/Instructions.h:2118
Method
isSingleValueType
Return true if the type is a valid type for a register in codegen. This includes all first-class types except struct and array types.
suite/synctools/tablegen/include/llvm/IR/Type.h:248
Method
isSlowDivBypassed
Returns true if target has indicated at least one type should be bypassed.
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:532
Method
isSoloInstruction
Return true if instruction MI can not be packetized with any other instruction, which means that MI itself is a packet.
suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h:167
Method
isSourceOfDivergence
suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h:264
Method
isSpecialKey
suite/synctools/tablegen/include/llvm/IR/ModuleSummaryIndex.h:274
Function
isSpeculatable
Determine if the call has sideeffects.
suite/synctools/tablegen/include/llvm/IR/Function.h:583
Method
isSpillSlotObjectIndex
Returns true if the specified index corresponds to a spill slot.
suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h:685
Method
isSpillable
isSpillable - Can this interval be spilled?
suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h:813
Method
isSpilledToReg
suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h:74
Method
isSplat
suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h:1520
Method
isSplit
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:131
Method
isSplit
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus, the point materialized, the point will not require split
suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h:188
Method
isSplit
suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h:267
Method
isSplit
suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h:304
Method
isSplitEnd
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:134
Method
isSrcAligned
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:178
Method
isStack
suite/synctools/tablegen/include/llvm/CodeGen/PseudoSourceValue.h:68
Method
isStackIdSafeForLocalArea
This method returns whether or not it is safe for an object with the given stack id to be bundled into the local area.
suite/synctools/tablegen/include/llvm/CodeGen/TargetFrameLowering.h:133
Method
isStackRealignable
isStackRealignable - This method returns whether the stack can be realigned.
suite/synctools/tablegen/include/llvm/CodeGen/TargetFrameLowering.h:122
Method
isStackSlot
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable that normally holds a register. isStackSlot() retur
suite/synctools/tablegen/include/llvm/CodeGen/Register.h:44
Method
isStackSlotCopy
Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect. Provide the identity of the two frame
suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h:336
Method
isStatepointSpillSlotObjectIndex
suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h:691
Method
isStaticMember
suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h:741
Method
isStoreBitCastBeneficial
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:583
Method
isStoreToStackSlot
If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with th
suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h:300
Method
isStoreToStackSlotPostFE
Check for post-frame ptr elimination stack locations as well. This uses a heuristic, so it isn't reliable for correctness.
suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h:318
Method
isStrictFP
Determine if the call requires strict floating point semantics.
suite/synctools/tablegen/include/llvm/IR/InstrTypes.h:1819
Method
isStrictFPEnabled
Return true if the target support strict float operation
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:329
Method
isStrictFPOpcode
Test if this node is a strict floating point pseudo-op.
suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h:665
Method
isStrictPredicate
@returns true if the comparison predicate is strict, false otherwise. Determine if this instruction is using an strict comparison predicate.
suite/synctools/tablegen/include/llvm/IR/InstrTypes.h:867
Method
isStrongDefinitionForLinker
Returns true if this global's definition will be the one chosen by the linker. NB! Ideally this should not be used at the IR level at all. If you're
suite/synctools/tablegen/include/llvm/IR/GlobalValue.h:553
Method
isStruct
suite/synctools/tablegen/include/llvm/IR/GetElementPtrTypeIterator.h:111
Method
isStructTy
True if this is an instance of StructType.
suite/synctools/tablegen/include/llvm/IR/Type.h:211
Method
isSubClassOf
suite/synctools/tablegen/include/llvm/TableGen/Record.h:1648
Method
isSubregFoldable
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). For example, X86 may want to return tru
suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h:1080
Method
isSubregToReg
suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h:1273
Method
isSucc
Tests if node N is a successor of this node.
suite/synctools/tablegen/include/llvm/CodeGen/ScheduleDAG.h:439
Method
isSupportedFixedPointOperation
Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. If not, the operation
suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h:1088
Method
isSupportedStackID
suite/synctools/tablegen/include/llvm/CodeGen/TargetFrameLowering.h:424
Method
isSwiftAsync
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:99
Method
isSwiftError
Return true if this alloca is used as a swifterror argument to a call.
suite/synctools/tablegen/include/llvm/IR/Instructions.h:150
Method
isSwiftError
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:102
Method
isSwiftSelf
suite/synctools/tablegen/include/llvm/CodeGen/TargetCallingConv.h:96
Method
isSymbol
isSymbol - Tests if this is a MO_ExternalSymbol operand.
suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h:341
Method
isSynthetic
suite/synctools/tablegen/include/llvm/IR/Function.h:265
Function
isT2SOImmTwoPartVal
arch/ARM/ARMAddressingModes.h:367
Method
isTailCall
suite/synctools/tablegen/include/llvm/IR/Instructions.h:1669
Method
isTailCall
Determines whether \p Inst is a tail call instruction. Override this method on targets that do not properly set MCID::Return and MCID::Call on tail ca
suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h:1873
Method
isTargetIndex
isTargetIndex - Tests if this is a MO_TargetIndex operand.
suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h:335
Method
isTargetMemoryOpcode
Test if this node has a target-specific memory-referencing opcode (in the \<target\>ISD namespace and greater than FIRST_TARGET_MEMORY_OPCODE).
suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h:646
Method
isTargetOpcode
Test if this node has a target-specific opcode (in the \<target\>ISD namespace).
suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h:632
Method
isTargetOpcode
suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h:1141
Function
isTargetSpecificOpcode
Check whether the given Opcode is a target-specific opcode.
suite/synctools/tablegen/include/llvm/CodeGen/TargetOpcodes.h:36
Method
isTargetStrictFPOpcode
Test if this node has a target-specific opcode that may raise FP exceptions (in the \<target\>ISD namespace and greater than FIRST_TARGET_STRICTFP_OPC
suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h:639
Method
isTemplateArg
Is this a template argument?
suite/synctools/tablegen/include/llvm/TableGen/Record.h:1450
Method
isTemplateArg
suite/synctools/tablegen/include/llvm/TableGen/Record.h:1592
Method
isTemporary
suite/synctools/tablegen/include/llvm/IR/Metadata.h:1006
Method
isThreadLocal
If the value is "Thread Local", its value isn't shared by the threads.
suite/synctools/tablegen/include/llvm/IR/GlobalValue.h:244
Function
isThumbImm16ShiftedVal
isThumbImm16ShiftedVal - Return true if the specified value can be obtained by left shifting a 16-bit immediate.
arch/ARM/ARMAddressingModes.h:269
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