Return true if the object was pre-allocated into the local block.

isOnRegUseList - Return true if this operand is on a register use/def list or false if not. This can only be called for register operands that are pa

Return true if the operand at index \p Idx is a bundle operand that has tag ID \p ID.

Return true if operand \p OpIdx is a subregister index.

Return true if the operation uses custom lowering, regardless of whether the type is legal or not.

Return true if the specified operation is legal on this target.

Returns true if MI is a candidate for move elimination. A candidate for move elimination may be optimized out at register renaming stage. Subtargets

Returns true if the specified value is the overflow result from one of the overflow intrinsic nodes.

Return true if this is an overloaded type for TableGen.

Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC-relative addressing. PC-relative addressing

Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been eliminated). PHI-defs begin at a block boundary, al

isPHIJoin - Return true if Reg is a phi join register.

Return true if this is powerpc long double.

Determine whether this argument is passed by value, in an alloca, or is preallocated.

Determine whether passing undef to this argument is undefined behavior. If passing undef to this argument is UB, passing poison is UB as well because

Return true if the specified register number is in the physical register namespace.

isPointerIntoBucketsArray - Return true if the specified pointer points somewhere into the ValueMap's array of buckets (i.e. either to a key or value

True if the instruction represents a position in the function.

Return true for post-incremented instructions.

\returns true if \p Opcode is an optimization hint opcode which is not supposed to appear after ISel.

Return true if this is an instruction that should go through the usual legalization steps.

Tests if node N is a predecessor of this node.

Return true if this node is a predecessor of N. NOTE: Implemented on top of hasPredecessor and every bit as expensive. Use carefully.

Return true if this instruction has a predicate operand that controls execution. It may be set to 'always', or may be set to other values. There ar

Return true if the specified instruction can be predicated. By default, this returns true for every instruction with a PredicateOperand.

Returns true if the instruction is already predicated.

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

A function will have the "coroutine.presplit" attribute if it's a coroutine and has not gone through full CoroSplit pass.

Check if the no-CSR optimisation is profitable for the given function.

Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enabl

Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the p

Return true if it's profitable to unpredicate one side of a 'diamond', i.e. two sides of if-else predicated on mutually exclusive predicates. e.g. sub

isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers. Register classes like GR32_NOSP are not proper sub-cla

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

For the regular discriminator, it stands for all empty components if all the lowest 3 bits are non-zero and all higher 29 bits are unused(zero by defa

Check if this is rvalue-reference-qualified. Return true if this subprogram is a C++11 rvalue-reference-qualified non-static member function (void fo

isReachableFromEntry - Return true if A is dominated by the entry block of the function containing it.

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually triv

Lets target to control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y), c1) where N0 is (op x, c1) and N1 is y. By defaul

isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = R

Return true if the use operand of the specified index is tied to a def operand. It also returns the def operand index by reference if DefOpIdx is not

Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline asse

isRegister - Returns true if this is a normal register use/def slot. Note that early-clobber slots may also be used for uses and defs.

Return true if the predicate is relational (not EQ or NE).

@returns true if the predicate is relational (not EQ or NE). Determine if this a relational predicate.

Return true if the predicate is relational (not EQ or NE).

isReserved - Returns true when PhysReg is a reserved register. Reserved registers may belong to an allocatable register class, but the target has exp

Returns true if a register is reserved. It is never "unused".

Is the scheduled region resource limited vs. latency limited.