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Function npyv_load_till_s32

numpy/core/src/common/simd/vec/memory.h:203–240  ·  view source on GitHub ↗

* Partial Load *********************************/ / 32

Source from the content-addressed store, hash-verified

201 *********************************/
202//// 32
203NPY_FINLINE npyv_s32 npyv_load_till_s32(const npy_int32 *ptr, npy_uintp nlane, npy_int32 fill)
204{
205 assert(nlane > 0);
206 npyv_s32 vfill = npyv_setall_s32(fill);
207#ifdef NPY_HAVE_VX
208 const unsigned blane = (nlane > 4) ? 4 : nlane;
209 const npyv_u32 steps = npyv_set_u32(0, 1, 2, 3);
210 const npyv_u32 vlane = npyv_setall_u32(blane);
211 const npyv_b32 mask = vec_cmpgt(vlane, steps);
212 npyv_s32 a = vec_load_len(ptr, blane*4-1);
213 a = vec_sel(vfill, a, mask);
214#else
215 npyv_s32 a;
216 switch(nlane) {
217 case 1:
218 a = vec_insert(ptr[0], vfill, 0);
219 break;
220 case 2:
221 a = (npyv_s32)vec_insert(
222 *npyv__ptr2u64(ptr), (npyv_u64)vfill, 0
223 );
224 break;
225 case 3:
226 vfill = vec_insert(ptr[2], vfill, 2);
227 a = (npyv_s32)vec_insert(
228 *npyv__ptr2u64(ptr), (npyv_u64)vfill, 0
229 );
230 break;
231 default:
232 return npyv_load_s32(ptr);
233 }
234#endif
235#if NPY_SIMD_GUARD_PARTIAL_LOAD
236 volatile npyv_s32 workaround = a;
237 a = vec_or(workaround, a);
238#endif
239 return a;
240}
241// fill zero to rest lanes
242NPY_FINLINE npyv_s32 npyv_load_tillz_s32(const npy_int32 *ptr, npy_uintp nlane)
243{

Callers 1

npyv_load_tillz_s32Function · 0.70

Calls 1

npyv__ptr2u64Function · 0.85

Tested by

no test coverage detected