fill zero to rest lanes
| 240 | } |
| 241 | // fill zero to rest lanes |
| 242 | NPY_FINLINE npyv_s32 npyv_load_tillz_s32(const npy_int32 *ptr, npy_uintp nlane) |
| 243 | { |
| 244 | #ifdef NPY_HAVE_VX |
| 245 | unsigned blane = (nlane > 4) ? 4 : nlane; |
| 246 | return vec_load_len(ptr, blane*4-1); |
| 247 | #else |
| 248 | return npyv_load_till_s32(ptr, nlane, 0); |
| 249 | #endif |
| 250 | } |
| 251 | //// 64 |
| 252 | NPY_FINLINE npyv_s64 npyv_load_till_s64(const npy_int64 *ptr, npy_uintp nlane, npy_int64 fill) |
| 253 | { |
nothing calls this directly
no test coverage detected